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  • richardmitnick 4:35 pm on February 15, 2019 Permalink | Reply
    Tags: EuroHPC JU will be the owner of the precursors to exascale supercomputers it will acquire, EuroHPC JU-European High Performance Computing Joint Undertaking, EuroHPC Takes First Steps Towards Exascale, insideHPC,   

    From insideHPC: “EuroHPC Takes First Steps Towards Exascale” 

    From insideHPC

    1

    The European High Performance Computing Joint Undertaking (EuroHPC JU) has launched its first calls for expressions of interest, to select the sites that will host the Joint Undertaking’s first supercomputers (petascale and precursor to exascale machines) in 2020.

    “Deciding where Europe will host its most powerful petascale and precursor to exascale machines is only the first step in this great European initiative on high performance computing,” said Mariya Gabriel, Commissioner for Digital Economy and Society. “Regardless of where users are located in Europe, these supercomputers will be used in more than 800 scientific and industrial application fields for the benefit of European citizens.”

    Supercomputing, also known as high performance computing (HPC), involves thousands of processors working in parallel to analyse billions of pieces of data in real time, performing calculations much faster than a normal computer, and enabling scientific and industrial challenges of great scale and complexity to be met. The EuroHPC JU has the target of equipping the EU by the end of 2020 with a world-class supercomputing infrastructure that will be available to users from academia, industry and small and medium-sized enterprises, and the public sector. These new European supercomputers will also support the development of leading scientific, public sector and industrial applications in many domains, including personalised medicine, bio-engineering, weather forecasting and tackling climate change, discovering new materials and medicines, oil and gas exploration, designing new planes and cars, and smart cities.

    The EuroHPC JU was established in 2018, with the participation of 25 European countries and the European Commission, and has its headquarters in Luxembourg. By 2020, its objective is to acquire and deploy in the EU at least two supercomputers that will rank among the top five in the world, and at least two others that today would be in the top 25 machines globally. These supercomputers will be hosted and operated by hosting entities (existing national supercomputing centres) located in different Member States participating in the EuroHPC JU.

    To this purpose, the EuroHPC JU has now opened two calls for expressions of interest:

    Call for hosting entities for petascale supercomputers (with a performance level capable of executing at least 1015 operations per second, or 1 Petaflop)
    Call for hosting entities for precursor to exascale supercomputers (with a performance level capable of executing more than 150 Petaflops).

    In addition to these plans, the EuroHPC JU aims to acquire by 2022/23 exascale supercomputers, capable of 1018 operations per second, with at least one being based on European HPC technology.

    In the acquisition of the petascale supercomputers, the EuroHPC JU’s financial contribution, from the EU’s budget, will be up to EUR 30 million, covering up to 35% of the acquisition costs. All the remaining costs of the supercomputers will be covered by the country where the hosting entity is established.

    For the precursor to exascale supercomputers, the EuroHPC JU’s financial contribution, from the EU’s budget, will be up to EUR 250 million and will enable the JU to fund up to 50% of the acquisition costs, and up to 50% of the operating costs of the supercomputers. The hosting entities and their supporting countries will cover the remaining acquisition and operating costs. The EuroHPC JU will be the owner of the precursors to exascale supercomputers it will acquire.

    See the full article here .

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    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
    2825 NW Upshur
    Suite G
    Portland, OR 97239

    Phone: (503) 877-5048

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  • richardmitnick 1:48 pm on February 12, 2019 Permalink | Reply
    Tags: insideHPC, ,   

    From insideHPC: “Moving Mountains of Data at NERSC” 

    From insideHPC

    1
    NERSC’s Wayne Hurlbert (left) and Damian Hazen (right) are overseeing the transfer of 43 years’ worth of NERSC data to new tape libraries at Shyh Wang Hall. Image: Peter DaSilva

    NERSC

    NERSC Cray Cori II supercomputer at NERSC at LBNL, named after Gerty Cori, the first American woman to win a Nobel Prize in science


    LBL NERSC Cray XC30 Edison supercomputer


    The Genepool system is a cluster dedicated to the DOE Joint Genome Institute’s computing needs. Denovo is a smaller test system for Genepool that is primarily used by NERSC staff to test new system configurations and software.

    NERSC PDSF


    PDSF is a networked distributed computing cluster designed primarily to meet the detector simulation and data analysis requirements of physics, astrophysics and nuclear science collaborations.

    Researchers at NERSC face the daunting task of moving 43 years worth of archival data across the network to new tape libraries, a whopping 120 Petabytes!

    When NERSC relocated from its former home in Oakland to LBNL in 2015, not everything came with. The last remaining task in the heroic effort of moving the supercomputing facility and all of its resources is 43 years of archival data that’s stored on thousands of high performance tapes in Oakland. Those 120 petabytes of experimental and simulation data have to be electronically transferred to new tape libraries at Berkeley Lab, a process that will take up to two years—even with an ESnet 400 Gigabit “superchannel” now in place between the two sites.

    Tape for archival storage makes sense for NERSC and is a key component of NERSC’s storage hierarchy. Tape provides long-term, high capacity stable storage and only consumes power when reading or writing, making it a cost-effective and environmentally friendly storage solution. And the storage capacity of a tape cartridge exceeds that of more commonly known hard disk drives.

    “Increasing hard disk drive capacity has become more and more difficult as manufacturers need to pack more data into a smaller and smaller area, whereas today’s tape drives are leveraging technology developed for disks a decade ago,” said Damian Hazen, NERSC’s storage systems group lead. Hazen points out that tape storage technology has receded from the public eye in part because of capacity online data storage services provided by the likes of Google, Microsoft, and Amazon, and that disk does work well for those with moderate storage needs. But, unbeknownst to most users, these large storage providers also include tape in their storage strategy.”

    “Moderate” does not describe NERSC’s storage requirements. With data from simulations run on NERSC’s Cori supercomputer, and experimental and observational data coming from facilities all over the U.S. and abroad, the NERSC users send approximately 1.5 petabytes of data each month to the archive.

    “Demands on the NERSC archive grow every year,” Hazen said. “With the delivery of NERSC’s next supercomputer Perlmutter in 2020, and tighter integration of computational facilities like NERSC with local and remote experimental facilities like ALS and LCLS-II, this trend will continue.”

    [Perlmutter supercomputer honors Nobel laureate Saul Perlmutter for providing evidence that the expansion of the universe is accelerating.]

    3

    LBNL/ALS

    SLAC LCLS-II

    Environmental Challenges

    To keep up with the data challenges, the NERSC storage group continuously refreshes the technology used in the archive. But in relocating the archive to the environmentally efficient Shyh Wang Hall, there was an additional challenge. The environmental characteristics of the new energy-efficient building meant that NERSC needed to deal with more substantial changes in temperature and humidity in the computer room. This wasn’t good news for tape, which requires a tightly controlled operating environment, and meant that the libraries in Oakland could not just be picked up and moved to Berkeley Lab. New technology emerged at just the right time in the form of an environmentally isolated tape library, which uses built-in environmental controls to maintain an ideal internal environment for the tapes. NERSC deployed two full-sized, environmentally self-contained libraries last fall. Manufactured by IBM, the new NERSC libraries are currently the largest of this technology in the world.

    3
    NERSC’s new environmentally self-contained tape libraries use a specialized robot to retrieve archival data tapes. Image: Peter DaSilva

    “The new libraries solved two problems: the environmental problem, which allowed us to put the tape library right on the computer room floor, and increasing capacity to keep up with growth as we move forward,” said Wayne Hurlbert, a staff engineer in NERSC’s storage systems group. Tape cartridge capacity doubles roughly every two to three years, with 20 terabyte cartridges available as of December 2018.”

    The newer tape cartridges have three times the capacity of the old, and the archive libraries can store a petabyte per square foot. With the new system in place, data from the tape drives in Oakland is now streaming over to the tape archive libraries in the Shyh Wang Hall computer room via the 400 Gigabit link that ESnet built three years ago to connect the two data centers together. It was successfully used to transfer file systems between the two sites without any disruption to users. As with the file system move, the archive data transfer will be largely transparent to users.

    Even with all of this in place, it will still take about two years to move 43 years’ worth of NERSC data. Several factors contribute to this lengthy copy operation, including the extreme amount of data to be moved and the need to balance user access to the archive.

    “We’re very cautious about this,” Hurlbert said. “We need to preserve this data; it’s not infrequent for researchers to need to go back to their data sets, often to use modern techniques to reanalyze. The archive allows us to safeguard irreplaceable data generated over decades; the data represents millions of dollars of investment in computational hardware and immense time, effort, and scientific results from researchers around the world.”

    See the full article here .

    five-ways-keep-your-child-safe-school-shootings

    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
    2825 NW Upshur
    Suite G
    Portland, OR 97239

    Phone: (503) 877-5048

     
  • richardmitnick 12:35 pm on February 12, 2019 Permalink | Reply
    Tags: , CANDLE (CANcer Distributed Learning Environment) framework, , insideHPC,   

    From insideHPC: “Argonne ALCF Looks to Singularity for HPC Code Portability” 

    From insideHPC

    February 10, 2019

    Over at Argonne, Nils Heinonen writes that Researchers are using the open source Singularity framework as a kind of Rosetta Stone for running supercomputing code most anywhere.

    Scaling code for massively parallel architectures is a common challenge the scientific community faces. When moving from a system used for development—a personal laptop, for instance, or even a university’s computing cluster—to a large-scale supercomputer like those housed at the Argonne Leadership Computing Facility [see below], researchers traditionally would only migrate the target application: the underlying software stack would be left behind.

    To help alleviate this problem, the ALCF has deployed the service Singularity. Singularity, an open-source framework originally developed by Lawrence Berkeley National Laboratory (LBNL) and now supported by Sylabs Inc., is a tool for creating and running containers (platforms designed to package code and its dependencies so as to facilitate fast and reliable switching between computing environments)—albeit one intended specifically for scientific workflows and high-performance computing resources.

    “here is a definite need for increased reproducibility and flexibility when a user is getting started here, and containers can be tremendously valuable in that regard,” said Katherine Riley, Director of Science at the ALCF. “Supporting emerging technologies like Singularity is part of a broader strategy to provide users with services and tools that help advance science by eliminating barriers to productive use of our supercomputers.”

    2
    This plot shows the number of events ATLAS events simulated (solid lines) with and without containerization. Linear scaling is shown (dotted lines) for reference.

    The demand for such services has grown at the ALCF as a direct result of the HPC community’s diversification.

    When the ALCF first opened, it was catering to a smaller user base representative of the handful of domains conventionally associated with scientific computing (high energy physics and astrophysics, for example).

    ANL ALCF Cetus IBM supercomputer

    ANL ALCF Theta Cray supercomputer

    ANL ALCF Cray Aurora supercomputer

    ANL ALCF MIRA IBM Blue Gene Q supercomputer at the Argonne Leadership Computing Facility

    HPC is now a principal research tool in new fields such as genomics, which perhaps lack some of the computing culture ingrained in certain older disciplines. Moreover, researchers tackling problems in machine learning, for example, constitute a new community. This creates a strong incentive to make HPC more immediately approachable to users so as to reduce the amount of time spent preparing code and establishing migration protocols, and thus hasten the start of research.

    Singularity, to this end, promotes strong mobility of compute and reproducibility due to the framework’s employment of a distributable image format. This image format incorporates the entire software stack and runtime environment of the application into a single monolithic file. Users thereby gain the ability to define, create, and maintain an application on different hosts and operating environments. Once a containerized workflow is defined, its image can be snapshotted, archived, and preserved for future use. The snapshot itself represents a boon for scientific provenance by detailing the exact conditions under which given data were generated: in theory, by providing the machine, the software stack, and the parameters, one’s work can be completely reproduced. Because reproducibility is so crucial to the scientific process, this capability can be seen as one of the primary assets of container technology.

    ALCF users have already begun to take advantage of the service. Argonne computational scientist Taylor Childers (in collaboration with a team of researchers from Brookhaven National Laboratory, LBNL, and the Large Hadron Collider’s ATLAS experiment) led ASCR Leadership Computing Challenge and ALCF Data Science Program projects to improve the performance of ATLAS software and workflows on DOE supercomputers.

    CERN/ATLAS detector

    Every year ATLAS generates petabytes of raw data, the interpretation of which requires even larger simulated datasets, making recourse to leadership-scale computing resources an attractive option. The ATLAS software itself—a complex collection of algorithms with many different authors—is terabytes in size and features manifold dependencies, making manual installation a cumbersome task.

    The researchers were able to run the ATLAS software on Theta inside a Singularity container via Yoda, an MPI-enabled Python application the team developed to communicate between CERN and ALCF systems and ensure all nodes in the latter are supplied with work throughout execution. The use of Singularity resulted in linear scaling on up to 1024 of Theta’s nodes, with event processing improved by a factor of four.

    “All told, with this setup we were able to deliver to ATLAS 65 million proton collisions simulated on Theta using 50 million core-hours,” said John Taylor Childers from ALCF.

    Containerization also effectively circumvented the software’s relative “unfriendliness” toward distributed shared file systems by accelerating metadata access calls; tests performed without the ATLAS software suggested that containerization could speed up such access calls by a factor of seven.

    While Singularity can present a tradeoff between immediacy and computational performance (because the containerized software stacks, generally speaking, are not written to exploit massively parallel architectures), the data-intensive ATLAS project demonstrates the potential value in such a compromise for some scenarios, given the impracticality of retooling the code at its center.

    Because containers afford users the ability to switch between software versions without risking incompatibility, the service has also been a mechanism to expand research and try out new computing environments. Rick Stevens—Argonne’s Associate Laboratory Director for Computing, Environment, and Life Sciences (CELS)—leads the Aurora Early Science Program project Virtual Drug Response Prediction. The machine learning-centric project, whose workflow is built from the CANDLE (CANcer Distributed Learning Environment) framework, enables billions of virtual drugs to be screened singly and in numerous combinations while predicting their effects on tumor cells. Their distribution made possible by Singularity containerization, CANDLE workflows are shared between a multitude of users whose interests span basic cancer research, deep learning, and exascale computing. Accordingly, different subsets of CANDLE users are concerned with experimental alterations to different components of the software stack.

    CANDLE users at health institutes, for instance, may have no need for exotic code alterations intended to harness the bleeding-edge capabilities of new systems, instead requiring production-ready workflows primed to address realistic problems,” explained Tom Brettin, Strategic Program Manager for CELS and a co-principal investigator on the project. Meanwhile, through the support of DOE’s Exascale Computing Project, CANDLE is being prepared for exascale deployment.

    Containers are relatively new technology for HPC, and their role may well continue to grow. “I don’t expect this to be a passing fad,” said Riley. “It’s functionality that, within five years, will likely be utilized in ways we can’t even anticipate yet.”

    See the full article here .

    five-ways-keep-your-child-safe-school-shootings

    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
    2825 NW Upshur
    Suite G
    Portland, OR 97239

    Phone: (503) 877-5048

     
  • richardmitnick 12:16 pm on February 8, 2019 Permalink | Reply
    Tags: $3 billion investment, IBM Research AI Hardware Center, IBM Research AI Hardware Center to Drive Next-Generation AI Chips, insideHPC, Partnerships within an open ecosystem are key to advancing hardware and software innovation that are the foundation of AI, Shrink semiconductors to 7 nanometers and beyond, SUNY Polytechnic campus in Albany New York, The multi-billion dollar Albany NanoTech Complex highlighted by the institution’s Center for Semiconductor Research (CSR) a $500 million program that also includes the world’s leading nanoelectron   

    From insideHPC: “IBM Research AI Hardware Center to Drive Next-Generation AI Chips” 

    From insideHPC

    February 7, 2019

    1
    An IBM chip comprising several Analog AI devices used for in-memory computing.

    Today IBM announced an ambitious plan to create a global research hub to develop next-generation AI hardware and expand their joint research efforts in nanotechnology. As part of a $3 billion commitment, the IBM Research AI Hardware Center will be the nucleus of a new ecosystem of research and commercial partners collaborating with IBM researchers to further accelerate the development of AI-optimized hardware innovations.

    IBM headquarters for the AI Hardware Center will be on the SUNY Polytechnic campus in Albany, New York, and the Center will advance a range of technologies from chip-level devices, materials and architecture to the software supporting AI workloads. These efforts will push the limits of chip technology needed to meet the emerging demands of cloud computing, Big Data, and cognitive computing systems.

    “The groundbreaking work that these engineers will conduct at SUNY Polytechnic Institute reflects IBM’s long-term commitment to inventing the future of microelectronics,” said Dr. John Kelly, Senior Vice President, Solutions Portfolio and Research at IBM. “The IBMers working at SUNY Poly possess unique skills and capabilities, positioning our company to drive development of the next generation of chips and to fuel a new era of computing.”

    2
    IBM Research AI Hardware Center is developing a roadmap for 1,000x improvement in AI compute performance efficiency over the next decade, with a pipeline of Digital AI Cores and Analog AI Cores.

    The $3 billion investment that IBM announced in July 2014 focuses on the development of basic materials science to make it possible to shrink semiconductors to 7 nanometers and beyond, as well as support research into completely new areas beyond traditional silicon architectures, such as synaptic computing, quantum devices, carbon nanotubes, and photonics, that could transform computing of all kinds.

    “Partnerships within an open ecosystem are key to advancing hardware and software innovation that are the foundation of AI. New IBM Research AI Hardware Center partnerships announced today will aid in those continuing efforts. Samsung is a strategic IBM partner in both manufacturing and research. Mellanox Technologies is a leading supplier of high-performance, end-to-end smart interconnect solutions that accelerate many of the world’s leading AI and machine learning platforms. Synopsys is the leader in software platforms, emulation and prototyping solutions, and IP for developing the high-performance silicon chips and secure software applications that are driving advancements in AI.”

    3
    IBM analog AI cores are part of an in-memory computing approach in performance efficiency which improves by suppressing the so-called Von Neuman bottleneck by eliminating data transfer to and from memory. Deep neural networks are mapped to analog cross point arrays and new non-volatile material characteristics are toggled to store network parameters in the cross points. Learn how this technology works in our live interactive demo.

    IBM and SUNY Poly have built a highly successful, globally recognized partnership at the multi-billion dollar Albany NanoTech Complex, highlighted by the institution’s Center for Semiconductor Research (CSR), a $500 million program that also includes the world’s leading nanoelectronics companies. The CSR is a long-term, multi-phase, joint R&D cooperative program on future computer chip technology. IBM was a founding member of Governor Andrew M. Cuomo’s Global 450 Consortium. It continues to provide student scholarships and fellowships at the university to help prepare the next generation of nanotechnology scientists, researchers and engineers.

    See the full article here .

    five-ways-keep-your-child-safe-school-shootings

    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
    2825 NW Upshur
    Suite G
    Portland, OR 97239

    Phone: (503) 877-5048

     
  • richardmitnick 3:51 pm on February 4, 2019 Permalink | Reply
    Tags: 'AI on the Fly’, , , Deep learning training, Delivering the high performance required in edge applications necessitates PCIe interconnectivity, High Performance Computing technology, insideHPC   

    From insideHPC: “High Performance Embedded Computing” 

    From insideHPC

    February 4, 2019
    Tim Miller

    1
    Tim Miller, President, SkyScale

    ‘AI on the Fly’ is the next killer application for High Performance Computing technology, but not many technology vendors have the range and skill set required to deliver effective solutions. The demand for these solutions is expanding rapidly with the ever increasing utility of artificial intelligence applications across a wide set of industries. The industries showing the largest proliferation of use cases for ‘AI on the Fly’ include deep learning, transportation, security, defense, manufacturing, retail, media and entertainment. Why is deep learning training only done in the datacenter and inferencing only done in the field when high performance computers that can be deployed in the field exist today? To identify hostile threats from planes or on the battlefield, predicting maintenance requirements at the oil field or piloting autonomous vehicles that learn on-the-fly instead of in a datacenter, these applications require local high performance processing. The need to acquire vast quantities of data at ever faster rates and then apply sophisticated analysis algorithms in real time requires all the traditional capabilities of high performance computing but now deployed at the edge and in mobile platforms.

    These edge applications have unique requirements over traditional embedded computing. There is no compromise possible in delivering high performance while maintaining efficient space, weight and power. Delivering the high performance required in edge applications necessitates PCIe interconnectivity providing the fast data highway between high speed processors, NVMe storage and compute accelerators using GPUs or application specific FPGAs. With the IBM Power 9 servers shipping now and AMD’s recent announcement of 7nm EPYC processors with Gen 4 PCIe available in servers later in 2019, this year is expected to see broadening deployments of PCIe Gen4 with signaling rates of 16GT/s per lane (16 gigatransfers per second). ‘AI on the Fly’ high performance applications will naturally demand this capability on the edge. Additionally, these solutions often require unique space and power saving form factors and specialized rugged enclosures.

    Providing AI or HPC solutions at the edge often require partnerships between OEMs with deep vertical market and application expertise and technology experts who can provide the underlying high performance building blocks and system design expertise. In Europe, OEMs developing solutions for edge and mobile HPC applications typically seek development partners who can not only provide the unique expertise required in power efficient HPC, PCIe interconnect, industrial computing, military systems, ruggedization and custom form factors, but who also have an established European capability. They need partners with brand recognition built on years of delivering high quality products in a responsive and cost effective manner and partners who can provide local design in capability and local pre- and post-sale project support.

    “Providing AI or HPC solutions at the edge often require partnerships between OEMs with deep vertical market and application expertise and technology experts who can provide the underlying high performance building blocks and system design expertise.”

    We believe that the recent combination of One Stop Systems and Bressner create an ideal European ‘AI on the Fly’ embedded HPC partner for OEMs addressing the growing HPC at the Edge and HPC on the move markets. OSS brings over 20 years of HPC and PCIe custom solution expertise providing solutions from airborne storage systems to ruggedized media servers. OSS is a partner with NVIDIA® and is an expert in developing specialized high performance systems based on NVIDIA GPUs. OSS is a leader in PCIe Gen4 with the first available 16 lane host adapter now and a full product line transition to Gen4 in 2019. Bressner has been a force in European industrial computing for over 25 years and has an established reputation with some of the largest industrial companies on the continent. The integration of the core competencies of these two companies and their global design capability now provide a premier partner in Europe to address the next killer application in High Performance embedded Computing: ‘AI on the Fly.’

    See the full article here .

    five-ways-keep-your-child-safe-school-shootings

    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
    2825 NW Upshur
    Suite G
    Portland, OR 97239

    Phone: (503) 877-5048

     
  • richardmitnick 12:15 pm on January 30, 2019 Permalink | Reply
    Tags: , insideHPC, Intel Xeon W-3175X processor released,   

    From insideHPC: “Intel steps up with 28 core Xeon Processor for High-End Workstations” 

    From insideHPC

    January 30, 2019

    1
    Intel Corporation has announced the release of the Intel Xeon W-3175X processor in January 2019. The Intel Xeon W-3175X is a 28-core workstation powerhouse built for select, highly-threaded and computing-intensive applications such as architectural and industrial design and professional content creation. (Credit: Tim Herman/Intel Corporation)

    Today Intel announced that their new Intel Xeon W-3175X processor is now available. This unlocked 28-core workstation powerhouse is built for select, highly-threaded and computing-intensive applications such as architectural and industrial design and professional content creation.

    “Built for handling heavily threaded applications and tasks, the Intel Xeon W-3175X processor delivers uncompromising single- and all-core world-class performance for the most advanced professional creators and their demanding workloads. With the most cores and threads, CPU PCIe lanes, and memory capacity of any Intel desktop processor, the Intel Xeon W-3175X processor has the features that matter for massive mega-tasking projects such as film editing and 3D rendering.”

    Other key features and capabilities:

    Intel Mesh Architecture, which delivers low latency and high data bandwidth between CPU cores, cache, memory and I/O while increasing the number of cores per processor– a critical need for the demanding, highly-threaded workloads of creators and experts.
    Intel Extreme Tuning Utility, a precision toolset that helps experienced overclockers optimize their experience with unlocked1processors.
    Intel Extreme Memory Profile, which simplifies the overclocking1experience by removing the guesswork of memory overclocking.
    Intel AVX-512 ratio offset and memory controller trim voltage control that allow for optimization of overclocking frequencies regardless of SSE or AVX workloads, and allow maximization of memory overclocking1.
    Intel Turbo Boost Technology 2.0 that delivers frequencies up to 4.3 GHz.
    Up to 68 platform PCIe lanes, 38.5 MB Intel Smart Cache, 6-channel DDR4 memory support with up to 512 GB at 2666 MHz, and ECC and standard RAS support power peripherals and high-speed tools.
    Intel C621 chipset based systems designed to support the Intel Xeon W-3175X processor allow professional content creators to achieve a new level of performance.
    Asetek 690LX-PN all-in-one liquid cooler, a custom created solution sold separately by Asetek, helps ensure the processor runs smoothly at both stock settings and while overclocking.

    The Intel Xeon W-3175X processor is available from system integrators that develop purpose-built desktop workstations.

    Intel Xeon W-3175X Specifications:

    Base Clock Speed (GHz): 3.1
    Intel Turbo Boost Technology 2.0 Maximum Single Core Turbo Frequency (GHz): 4.3
    Cores/Threads: 28/56
    TDP: 255W
    Intel Smart Cache: 38.5 MB
    Unlocked: Yes
    Platform PCIE Lanes: Up to 68
    Memory Support: Six Channels, DDR4-2666
    Standard RAS Support: Yes
    ECC Support: Yes
    RCP Pricing (USD 1K): $2,999

    See the full article here .

    five-ways-keep-your-child-safe-school-shootings

    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
    2825 NW Upshur
    Suite G
    Portland, OR 97239

    Phone: (503) 877-5048

     
  • richardmitnick 2:48 pm on January 29, 2019 Permalink | Reply
    Tags: ANSYS Discovery Live​ is a breakthrough in simulation experience, insideHPC, NVIDIA Quadro is the preeminent visual computing platform for professional 3D applications, NVIDIA Quadro Virtual Workstations now available on the Microsoft Azure Marketplace, Quadro vWS on ​NVIDIA Tesla GPUs​ from the Azure marketplace delivers the same benefits as on-premise VDI deployments   

    From insideHPC: “NVIDIA Quadro Comes to the Microsoft Azure Cloud” 

    From insideHPC

    January 29, 2019

    1
    With virtual workstations hosted in the datacenter, all compute, data and graphics reside on the server and clients receive only the pixel streams

    NVIDIA Quadro Virtual Workstations are now available on the Microsoft Azure Marketplace, enabling virtual workstation performance for more artists, engineers and designers.

    “Whether on a ​workstation​, ​data center server​ or​ ​virtual workspace​, NVIDIA Quadro is the preeminent visual computing platform for professional 3D applications. It enables incredible advancements, such as AI-accelerated rendering and real-time, interactive simulation. Now artists,​ ​designers and engineers ​can tap into the power of Quadro on any device, from any location through the cloud with Microsoft Azure. Starting today, Microsoft Azure cloud customers in industries like architecture, entertainment, oil and gas, and manufacturing can easily deploy the advanced GPU-accelerated capabilities of Quadro Virtual Workstation (Quadro vWS) whenever, wherever they need it.”

    With the Azure Marketplace, IT departments can spin up a GPU-accelerated virtual workstation in minutes from the Azure marketplace and enjoy the increased speed and agility. According to NVIDIA, these cloud customers can “scale up or down as business needs evolve, paying for only what they need on an hourly basis. The performance stays optimized with the latest drivers and upgrades.”

    “We’re focused on ​delivering the best and broadest range of GPU-accelerated capabilities in the public cloud,” said Talal Alqinaw, senior director of Microsoft Azure at Microsoft Corp. “NVIDIA Quadro vWS expands customer choice of GPU offerings on Azure to bring powerful professional workstations in the cloud to meet the needs of the most demanding applications from any device, anywhere.”

    Quadro vWS on ​NVIDIA Tesla GPUs​ from the Azure marketplace delivers the same benefits as on-premise VDI deployments. IT teams can support the most demanding users with 24GB of frame buffer per GPU. And they can deliver compute workloads from the cloud while also supporting professional workflows at peak performance.

    “ANSYS Discovery Live​ is a breakthrough in simulation experience,” said Justin Hendrickson, director of Product Management at ANSYS. “Powered by NVIDIA GPUs, it delivers an uncompromising interactive user experience. With Quadro vWS from the Azure marketplace, design engineers can quickly and easily interact with simulations in real time and iterate design alternatives remotely, on any device, resulting in significant cost and time reductions in the development phase.”

    How to Access NVIDIA Quadro on Azure

    To access NVIDIA Quadro on Azure, go to the Microsoft Azure Marketplace and select the NVIDIA Virtual Machine Image (VMI) with the Quadro Virtual Workstation software. You can configure it with the GPU, vCPU, memory and storage you need, without having to purchase any physical hardware and infrastructure.

    “IT only needs to install applications to get users up and running. For customers wanting a convenient, broad-scale cloud deployment, the Quadro vWS instances on Tesla GPUs are also supported on​ ​Windows Virtual Desktop​ on Azure. Windows Virtual Desktop delivers the best virtual desktop experience and remote apps to any device, bringing together Microsoft 365 and Azure to provide users with the only multi-session Windows 10 experience. The Windows 10 multi-session experience is only available on Azure.”

    See the full article here .

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    Please help promote STEM in your local schools.

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    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

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  • richardmitnick 11:11 pm on January 27, 2019 Permalink | Reply
    Tags: , ARM, , insideHPC, ,   

    From insideHPC: “Choice Comes to HPC: A Year in Processor Development” 

    From insideHPC

    January 27, 2019

    In this special guest feature, Robert Roe from Scientific Computing World writes that a whole new set of processor choices could shake up high performance computing.

    1

    With new and old companies releasing processors for the HPC market, there are now several options for high-performance server-based CPUs. This is being compounded by setbacks and delays at Intel opening up competition for the HPC CPU market.

    AMD has begun to find success on its EPYC brand of server CPUs. While market penetration will take some time, the company is starting to deliver competitive performance figures.

    IBM supplied the CPUs for the Summit system, which currently holds the top spot on the latest list of the Top500, a biannual list of the most powerful supercomputers.

    ORNL IBM AC922 SUMMIT supercomputer. Credit: Carlos Jones, Oak Ridge National Laboratory/U.S. Dept. of Energy

    While a single deployment is not a particularly strong measure of success, the Summit system has generated a lot of interest, five of the six Gordon Bell Prize finalists are running their applications on this system, which highlights the potential for this CPU – particularly when it is coupled with Nvidia GPUs.

    Arm is also gathering pace, as its technology partner’s ramp up production of Arm-based CPU systems for use in HPC deployments. Cavium (now Marvell) was an early leader in this market, delivering the ThunderX processor in 2015 and its follow up ThunderX2 was released for general availability in 2015.

    There are a number of smaller test systems using the Cavium chips, but the largest is the Astra supercomputer being developed at Sandia National Laboratories by HPE.

    HPE Vanguard Astra supercomputer with ARM technology at Sandia Labs

    This system is expected to deliver 2.3 Pflops of peak performance from 5,184 Thunder X2 CPUs.

    HPE, Bull and Penguin Computing have added the ThunderX2 CPU to its line-up of products available to HPC users. Coupled with the use of Allinea software tools, this is helping to give the impression of a viable ecosystem for HPC users.

    With many chip companies failing or struggling to generate a foothold in the HPC market over the last 10 to 20 years, it is important to provide a sustainable technology with a viable ecosystem for both hardware and software development. Once this has been achieved, Arm can begin to drive the market share.

    Fujitsu is another high-profile name committed to the development of Arm HPC technology. The company has been developing its own Arm-based processor for the Japanese Post K computer, in partnership with Riken, one of the largest Japanese research institutions.

    The A64FX CPU, developed by Fujitsu, will be the first processor to feature the Scalable Vector Extension (SVE), an extension of Armv8-A instruction set designed specifically for supercomputing architectures.

    It offers a number of features, including broad utility supporting a wide range of applications, massive parallelization through the Tofu interconnect, low power consumption, and mainframe-class reliability.

    Fujitsu reported in August that the processor would be capable of delivering a peak double precision (64 bit) floating point performance of over 2.7 Tflops, with a computational throughput twice that for single precision (32 bit), and four times that amount for half precision (16 bit).

    Trouble at the top

    Intel has been seen to struggle somewhat in recent months, as it has been reported that the next generation of its processors has been delayed due to supply issues and difficulty in the 10nm fabrication processes.

    The topic was addressed in August by Intel’s interim CEO Bob Swan, who reported healthy growth figures from the previous six months but also mentioned supply struggles and record investment processor development.

    “The surprising return to PC TAM growth has put pressure on our factory network. We’re prioritizing the production of Intel Xeon and Intel Core processors so that collectively we can serve the high-performance segments of the market. That said, supply is undoubtedly tight, particularly at the entry-level of the PC market. We continue to believe we will have at least the supply to meet the full-year revenue outlook we announced in July, which was $4.5 billion higher than our January expectations,” said Swan.

    Swan stated that the 10nm fabrication process was moving along with increased yields and volume production was planned for 2019: ‘We are investing a record $15 billion in capital expenditures in 2018, up approximately $1 billion from the beginning of the year. We’re putting that $1 billion into our 14nm manufacturing sites in Oregon, Arizona, Ireland and Israel. This capital, along with other efficiencies, is increasing our supply to respond to your increased demand.’

    “While Intel is undoubtedly the king of the hill when it comes to HPC processors – with more than 90 per cent of the Top500 using Intel-based technologies – the advances made by other companies, such as AMD, the re-introduction of IBM and the maturing Arm ecosystem are all factors that mean that Intel faces stiffer competition than it has for a decade.”

    The Rise of AMD

    The company had success in the headlines at the end of 2017 when the new range of server products was released but, as Greg Gibby, senior product manager of data centre products at AMD notes, he expects the company will begin to see some momentum as several ‘significant wins’ have already been completed.

    Microsoft has announced several cloud services that make use of AMD CPUs and the two socket products are also being deployed by Chinese companies such as Tencent for cloud-based services and Baidu has adopted both CPUs and GPUs from AMD to drive its machine learning and cloud workloads.

    AMD is generating huge revenue from its console partnerships with Sony and Microsoft.

    While these custom CPUs do not directly impact HPC technology, the revenue provided valuable time for AMD to get its server products ready. In 2018 the server line-up has been successful and AMD is rumored to announce 7nm products next year. If this comes to fruition AMD could further bolster its potential to compete in the HPC market.

    Gibby also noted that as performance is a key factor for many HPC users, it is important to get these products in front of the HPC user community.

    He said: “I believe that as we get customers testing the EPYC platform on their workloads, they see the significant performance advantages that EPYC brings to the market. I think that will provide a natural follow-through of us gaining share in that space.”

    One thing that could drive adoption of AMD products could be the memory bandwidth improvements which were a key feature of AMD when developing the EPYC CPUs. Memory bandwidth has long been a potential bottleneck for HPC applications, but this has become much more acute in recent years.

    In a recent interview with Scientific Computing World, Jack Wells, director of Science at Oak Ridge National Laboratory noted it as the number one user requirement when surveying the Oak Ridge HPC users.

    This was the first time that memory bandwidth had replaced peak node flops in the user requirements for this centre.

    While AMD was designing the next generation of its server-based CPU line, it took clear steps to design a processor that could meet the demands of modern workloads.

    Gibby noted that the CPU was not just designed to increase floating point performance, as there were key bottlenecks that the company identified, such as memory bandwidth that needed to be addressed.

    “Memory bandwidth was one of the key topics we looked at, so we put in eight memory channels on each socket,” said Gibby. “So in a dual socket system, you have 16 channels of memory, which gives really good memory bandwidth to keep the data moving in and out of the core.”

    “The other thing is on the I/O side. When you look at HPC specifically, you are looking at clusters with a lot of dependency on interconnects, whether it be InfiniBand or some other fabric.”

    “A lot of the time you have GPU acceleration in there as well, so we wanted to make sure that we had the I/O bandwidth to support this.”

    See the full article here .

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    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
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    Portland, OR 97239

    Phone: (503) 877-5048

     
  • richardmitnick 11:50 am on January 23, 2019 Permalink | Reply
    Tags: (NETL)-National Energy Technology Laboratory, Chemical looping reactors (CLRs), Exascale Computing Project's MFiX-Exa, insideHPC, Supercomputing Cleaner Power Plants   

    From insideHPC: “Supercomputing Cleaner Power Plants” 

    From insideHPC

    January 22, 2019

    1
    NETL’s laboratory-scale Chemical Looping Reactor (CLR) is used to test several oxygen-carrier materials (such as metal oxides) to determine their performance characteristics and durability. The CLR also generates data for validating computational models that will be used for designing larger-scale reactors. Courtesy: NETL

    Researchers are looking to HPC to help engineer cost-effective carbon capture and storage technologies for tomorrow’s power plants.

    One of the many novel combustion technologies that could greatly reduce the costs associated with the capture of carbon dioxide entails the use of what are called chemical looping reactors (CLRs). But CLRs have been demonstrated only in the laboratory and at small pilot scales, and they must be built to larger pilot and then industrial scales. Highly detailed, or high-fidelity, computer simulations could reduce the cost and technical risk as CLRs transition from research and development to first demonstrations in the 2025–2030 timeframe, to meet a CCS technology goal of the US Department of Energy.

    “An Exascale Computing Project effort, led by Madhava Syamlal of the National Energy Technology Laboratory (NETL), is building a new tool, called MFiX-Exa, that will enable the needed high-fidelity simulations. MFiX-Exa is a computational fluid dynamics–discrete element model (CFD-DEM) code designed to run efficiently on current and next-generation massively parallel supercomputing architectures. It is the latest creation based on the original MFiX code developed at NETL and is used widely in academia and industry.”

    By combining new algorithmic approaches and a new software infrastructure, MFiX-Exa will leverage future exascale machines to optimize CLRs. Exascale will provide 50 times more computational science and data analytic application power than is possible with DOE high-performance computing systems such as Titan at the Oak Ridge Leadership Computing Facility (OLCF) and Sequoia at Lawrence Livermore National Laboratory.

    ORNL Cray XK7 Titan Supercomputer, once the fastest in the world.

    LLNL Sequoia IBM Blue Gene Q petascale supercomputer

    “Tests have shown that the new MFiX-Exa algorithm reduces the computational time for the computational fluid dynamics calculations by 4x. The new algorithm is expected to perform even better in the ECP challenge problem simulation, which will use progressively more cores on an exascale machine.”

    2

    The Challenge Problem

    The MFiX-Exa efforts are directed at an ECP challenge problem that consists of a CFD-DEM simulation of NETL’s laboratory-scale CLR, which consists of a fuel reactor and an air reactor.

    Rather than air, the fuel reactor uses oxygen from solid oxygen carriers, such as metal oxides, to combust fossil fuels. The spent oxygen carrier is sent to the air reactor where it is regenerated with oxygen from air. The air reactor produces a hot air stream that is used to raise steam to drive a turbine for power generation; the fuel reactor produces gases from which CO2 can be easily captured. The regenerated oxygen carrier is returned to the fuel reactor, completing the chemical looping cycle.

    Chemical looping is a process to indirectly oxidize fuels with air, converting the chemical energy in fuels to thermal energy. In contrast to direct oxidation with air, carbon dioxide and nitrogen are in different exhaust streams. The carbon dioxide can be easily captured from the fuel reactor exhaust stream by condensing out the steam. Courtesy: NETL

    NETL’s laboratory-scale Chemical Looping Reactor (CLR) is used to test several oxygen-carrier materials (such as metal oxides) to determine their performance characteristics and durability. The CLR also generates data for validating computational models that will be used for designing larger-scale reactors. Courtesy: NETL

    The approximately 5 billion oxygen-carrier particles in the NETL CLR is a quantity 40 times greater than the number of particles simulated in the largest CFD-DEM studies reported in the research literature in which open-source or commercial codes are used. The challenge problem simulation is a stepping stone for large pilot- and industrial-scale simulations, which, however, are not in the scope of the current project.

    “Another aspect of the robustness of the MFiX-Exa challenge problem is that it requires the simulation of a longer operational time and the handling of a complex reactor with multiple flow regimes and chemical reactions. The team expects the challenge problem simulation to be 5x longer or more than studies reported in the research literature.”

    Project Advances and Successes

    The fundamental approach used to solve the ECP challenge problem is CFD-DEM. This methodology tracks individual particles using DEM while the gas flow is calculated with CFD. This method provides greater fidelity than the two-fluid model (TFM) and multiphase particle-in-cell (MP-PIC) methods currently popular in industry. By resolving the particles individually, the model does not need to use the approximations that reduce the fidelity of the TFM and MP-PIC methods.

    Although MFiX-Exa builds on the multiphase modeling expertise embodied in NETL’s MFiX code, the core methodology has been both re-designed and re-implemented. The foundation for MFiX-Exa is the AMReX software framework supported by the ECP Block-Structured Adaptive Mesh Refinement (AMR) Co-Design Center.

    In CFD-DEM, the entire volume of a simulated reactor is broken into a vast number of small contiguous volumes, over which the equations are solved. The collection of small volumes is called a mesh. The size of the mesh determines the fidelity of the simulation as well as the computational effort. AMR adjusts the computational effort locally to maintain a uniform level of accuracy throughout the reactor.

    MFiX-Exa uses more efficient algorithms than MFiX for reducing the computational time. A new CFD algorithm has been implemented in MFiX-Exa that leverages discretizations (finite elements of geometry) and linear solvers (pieces of mathematical software) already available through the AMReX framework.

    In CFD-DEM, the entire volume of a simulated reactor is broken into a vast number of small contiguous volumes, over which the equations are solved. The collection of small volumes is called a mesh. The size of the mesh determines the fidelity of the simulation as well as the computational effort. AMR adjusts the computational effort locally to maintain a uniform level of accuracy throughout the reactor.

    MFiX-Exa uses more efficient algorithms than MFiX for reducing the computational time. A new CFD algorithm has been implemented in MFiX-Exa that leverages discretizations (finite elements of geometry) and linear solvers (pieces of mathematical software) already available through the AMReX framework.

    “Tests have shown that the new MFiX-Exa algorithm reduces the computational time for the CFD calculations by 4x. The new algorithm is expected to perform even better in the challenge problem simulation, which will use progressively more cores on an exascale machine.”

    In the DEM, tracking the collisions between the particles and the reactor walls requires much computational time. A new algorithm that calculates the distance to the nearest wall once, stores that value, and reuses it for millions of repeated calculations, was implemented in MFiX-Exa. This improvement accelerated the DEM calculations for simple CLR geometries, and the team expects a greater speedup for the more complex CLR geometry.

    The finer the mesh, the greater the accuracy with which geometry and flow features can be simulated—but also greater is the computational time required.

    2
    National Energy Technology Laboratory Chemical Looping Reactor
    Chemical looping is a process to indirectly oxidize fuels with air, converting the chemical energy in fuels to thermal energy. In contrast to direct oxidation with air, carbon dioxide and nitrogen are in different exhaust streams. The carbon dioxide can be easily captured from the fuel reactor exhaust stream by condensing out the steam. Courtesy: NETL

    MFiX-Exa recently added the capability for local mesh refinement, which enables the use of a fine mesh near the walls that accurately resolves the reactor shape while not over-refining the interior of the reactor. Local mesh refinement will reduce the mesh size and, hence, the computational time required for the challenge problem.

    The project also implemented the ability to eliminate unneeded mesh in regions outside the CLR itself—that is, the empty space between the fuel and air reactors. For the challenge problem geometry, this will reduce the mesh size by 10x.

    The Collaborative Team

    MFiX-Exa has brought together researchers from NETL, Lawrence Berkeley National Laboratory (LBNL), and the University of Colorado (CU). NETL and CU represent more than six decades of experience in multiphase modeling and the MFiX code, while LBNL brings the same level of expertise in large-scale, multiscale multiphysics applications. In total, the MFiX-Exa team is characterized by more than 90 years of relevant experience and close collaborative ties: members interact daily, monthly, and yearly through Slack team message app channels, teleconferences, and all-hands meetings, respectively.

    Coming Next

    The most important next activity for the MFiX-Exa team is to ensure that MFiX-Exa code can run effectively on hybrid CPU/GPU architectures. The first stage of development has focused on running MFiX-Exa on multicore architectures such as the Cori supercomputer at the National Energy Research Scientific Computing Center.

    “The next stage will focus on running effectively on machines like the OLCF’s Summit system. Currently, the particle-particle collisions can be off-loaded to the GPUs, and work is in progress to migrate more of the algorithm to the GPUs to reap the benefit of their compute power.”

    Source: Exascale Computing Project

    See the full article here .

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    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
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    Suite G
    Portland, OR 97239

    Phone: (503) 877-5048

     
  • richardmitnick 10:43 am on January 23, 2019 Permalink | Reply
    Tags: France to Double Supercomputing Capacity with Jean Zay Ai System from HPE, IDRIS, insideHPC,   

    From insideHPC: “France to Double Supercomputing Capacity with Jean Zay Ai System from HPE” 

    From insideHPC

    January 22, 2019

    HPE is building a new Ai supercomputer for GENCI in France. Called Jean Zay, the 14 Petaflop system is part of an artificial intelligence initiative called for by President Macron to bolster the nation’s scientific and economic growth.

    Jean Zay HPE supercomputer France

    “By empowering the nation’s robust pool of talent with powerful compute technologies that target various, AI and analytics applications we see emerging, we believe France has the potential to be a driving force of AI efforts for the European market. At Hewlett Packard Enterprise, we continue to fuel the next frontier and unlock discoveries with our end-to-end HPC and AI offerings that hold a strong presence in France and have been further strengthened just in the past couple of years.”

    The initiative includes the HPE Artificial Intelligence Marketplace, a first-of-its-kind ecosystem in France of AI hardware and software solution providers for start-ups and enterprises, and the HPE HPC and AI Center of Excellence in Grenoble, a center of HPC and AI experts and tools to accelerate time-to-market of new products.

    “Once installed, the Jean Zay system will nearly double the supercomputing capacity of France.”

    The Jean Zay supercomputer will focus on research across fundamental physical sciences such as particle physics and cosmology, and biological sciences, to foster discoveries in fusion energy, space exploration and climate forecasting while also empowering applied research to optimize areas like combustion engines for automobiles and planes, pharmaceutical drugs, and solutions for natural disasters and disease pandemics.

    “Supercomputing has tremendous potential to accelerate innovation in AI for public and private sectors here in France and we are building a fast, powerful machine for GENCI to become France’s leading supercomputing research and development center for AI. With Jean Zay, we are enabling researchers to power faster, improved simulations like simulated events that can impact a nation’s environment, such as forest fires or a major earthquake’s aftershock. Detailed insight like this helps inform decision-makers to implement preventative tactics for more sustainable infrastructure that can reduce risks of destruction and fatalities.”

    The system will be open to France’s research communities to power scalable HPC and AI workloads, and lay a foundation for developing new methods to unlocking insight from larger, complex data, whether it be from physical particle samples or sensory data from IoT-enabled machines.

    Jean Zay will have a peak performance of 14 petaFLOPS and will be based on the HPE SGI 8600, a purpose-built high-performance computing (HPC) platform. It will converge the following powerful HPC and AI technologies to support machine learning and AI applications, along with improvement to traditional HPC workloads like modeling and simulation:

    CPU and GPU Parallel Computing: To run various compute processors in parallel with up to four 100 Gbs links per node, HPC is using a single HPC interconnection network
    Intel Omni-Path Architecture: powering 1,528 nodes of Intel Xeon Scalable processors for scalable compute performance and 261 nodes with 4 latest NVIDIA Tesla V100 32GB GPUs per node, for a total of 1044 GPUs.
    Faster Simulation with Flash Storage Technology: A read/write capacity of more than 300 GB per second will power faster simulations by integrating innovative flash storage capabilities with the HPE SGI 8600, an end-to-end HPC system, with support from DataDirect Network solutions.
    Improved Rendering Time with Cooling DLC (Direct Liquid Cooling): Through an HPC cooling solution, Jean Zay’s computing power is optimized to enable faster rendering times for simulations while also reducing energy consumption.

    Jean Zay will be installed at the IDRIS in June 2019 and put into production use by October 2019.

    IDRIS is the major centre of very high performance intensive numerical computation for the French National Centre for Scientific Research (CNRS). Together with the two other national centres, CINES (the computing centre for the French Ministry of Higher Education and Research) and the Very Large Computing Center (TGCC) of the French Alternative Energies and Atomic Energy Commission (CEA), and coordinated by GENCI (Grand Équipement National de Calcul Intensif), IDRIS participates in the installation of national computer resources for the use of government-funded research which requires extreme computing means.

    See the full article here .

    five-ways-keep-your-child-safe-school-shootings

    Please help promote STEM in your local schools.

    Stem Education Coalition

    Founded on December 28, 2006, insideHPC is a blog that distills news and events in the world of HPC and presents them in bite-sized nuggets of helpfulness as a resource for supercomputing professionals. As one reader said, we’re sifting through all the news so you don’t have to!

    If you would like to contact me with suggestions, comments, corrections, errors or new company announcements, please send me an email at rich@insidehpc.com. Or you can send me mail at:

    insideHPC
    2825 NW Upshur
    Suite G
    Portland, OR 97239

    Phone: (503) 877-5048

     
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